1. Field of the Invention
The present invention relates to a multiply-add unit of a data processing apparatus such as a micro-processor, and more particularly to a multiply-add unit for executing a multiply-add instruction for normalizing a calculation result at high speed, and a data processing apparatus using such a multiply-add unit.
2. Description of the Related Art
An example of a conventional microprocessor which executes a multiply-add instruction for normalizing a calculation result is PowerPC 603 described in "The PowerPC 603 Microprocessor: A High Performance, Low Power, Superscaler RISC Microprocessor" (digest of papers SPRING COMPCON '94, pp. 300 to 306).
This processor detects the leading digit from a value obtained after carry propagate addition. If the addend flows higher than the product, the digits of the flowed addend are aligned with the lower digits, and incremented by the carry from the lower digits.